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Elevating IoT Performance
To The Next Level

We power edge technology with the

most efficient architecture on the market.

VISION

The Future of Processors is Here.

Our patented CCISC MACROprocessor architecture provides higher performance

and lower power consumption compared to prevalent processor architectures in the marketplace.

 

This design outperforms the popular RISC-based architectures by executing compound-complex instructions, completing tasks in as much as 1/9th the time at the same clock speed.

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THE CONCEPT

A patented technology that conserves power without compromising performance.

COMPOUND COMPLEX INSTRUCTIONS IN A SINGLE CLOCK CYCLE

The efficiency of the MACROprocessor architecture results in a significant competitive advantage to IOT companies that produce edge sensors or applications where low power consumption commands a premium.

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APPLICATIONS ACROSS DIVERSE INDUSTRIES

  • Consumer IoT - wearables, security,  home appliances

  • Commercial IoT - healthcare, telecommunication, transportation industries

  • Industrial IoT - digital control systems, automation

  • Infrastructure IoT - sensors,   management systems

SCALABLE AND ADAPTABLE

Our processor can be utilized in any bus size (8-bit, 16-bit, 32-bit, …n-bit.) It has minimal support circuity and a small form-factor.

The clock speed can be changed to suit power usage goals and can be scaled with memory speed.

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WHY MOUNT TECHNOLOGY

A Novel Approach, Developed by Industry Veterans.

We are embedded hardware developers who have been designing systems with microprocessors and testing embedded hardware since the mid-1980s.

 

Our notable track record has served us in the design of our patented Compound Complex Instruction Set Computer Processor Architecture (CCISC) and the Compound Instruction concept.

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The MACROprocessor 
In Numbers

100 MHz

MAXIMUM INPUT CLOCK SPEED

617 uA

DYNAMIC POWER AT 10 MHz

8 bit

*

CORE DESIGN

up to 9X

PERFORMANCE GAIN

* scalable to any bus size

 as compared to competing architectures

PARTNERS

Backed By
Industry Leaders

It took years to develop and patent our revolutionary CCSIC MACROprocessor.

Along the way, we partnered with the best-in-class design, manufacturing and investment banking companies to tailor a product launch into select IoT market niches.

 

We bring the architecture. Our partners

bring it to life.

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TAIWAN SEMICONDUCTOR

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FALCON TRUST

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PACIFIC MICROCHIP

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HARVEST MANAGEMENT

PARTNERS

Kaveh Arabfakhry, Principal Design Engineer

"The Mount Technology CCSIC will revolutionize the way the industry
designs IoT edge devices."
  • Is the MACROprocessor patented?
    Yes, United States Patent #US 9,405,534 B2.
  • Can the MACROprocessor technology be licensed?
    Yes, Harvest Management Partners has been retained by Mount Technology for all IP and licensing matters. Please contact the HMP representative listed below.
  • Does Mount Technology manufacture the MACROprocessor?
    No, Mount Technology is a design house. Our prototype chips have been manufactured by Taiwan Semiconductor Manufacturing Company (TSMC).
  • How can I set up a technical presentation with Mount Technology engineers?
    You can organize a meeting with a Harvest Management Partners representative, who will facilitate a technical presentation with one of our engineers, by using the contact form or phone number listed below.
  • Where does the MACROprocessor name come from?
    The MACROprocessor is called such because it’s capable of so much functionality in a single instruction that it could be considered to be using macros of the instructions from other architectures.
  • Why is the MACROprocessor considered to be a “hybrid” CISC/RISC architecture?
    The MACROprocessor has all of the complex addressing modes that a CISC has, but maintains the flexibility, granularity, and single-clock nature of register-based RISC instructions.
  • How does the performance of the MACROprocessor compare to RISC/ARM architectures?
    While simple instructions done in registers on a RISC will match our architecture 1:1, any compound complex instructions can do in one cycle the work of 4 instructions that would take 9 cycles of execution on a RISC.
  • How flexible is the MACROprocessor?
    The proof-of-concept prototype we have developed is only 8-bit right now. However, the architectural concepts of the MACROprocessor can be utilized at any bus width and could potentially provide the same benefits to something as large as 64-bit. Since the architecture is all about efficiency, there does not need to be any sacrifice in power consumption for performance or vice-versa.
  • What kind of methods are used to maintain this efficiency?
    Very few industry standard speed-up methods have been used in this iteration of the architecture, leaving lots of room for improvement, such as the addition of pipelining.
  • What is the die size of the MACROprocessor?
    The proof-of-concept 8-bit prototype is 1.6mm x 1.6mm (projected size).
  • What are the Standby and Active power consumption rates of the MACROprocessor?
    Targeting 300uA for standby, 617uA for operating.
  • What applications will benefit the most from the MACROprocessor technology?
    Applications that need to maintain a higher throughput or bandwidth without burning a lot of power, or systems that need to use the lowest power possible. The architecture should be a great compliment to any battery-operated or energy-harvested applications, and will make for a great low-power compliment to a larger system as a co-processor or controller.
  • Is there a C Compiler and/or a standard development kit available for this architecture?
    We use a Standard C Compiler, modified to support our MACROprocessor. SDCC is a retargetable, optimizing Standard C (ANSI C89, ISO C99, ISO C11) compiler suite that targets 8-bit microprocessors. The Small Device C Compiler is a free-software, partially retargetable C compiler for 8-bit microcontrollers. It is distributed under the GNU General Public License. The package also contains an assembler, linker, simulator and debugger. It uses a SDCC Rev4.2.0 - C Complier.
  • How can I get my hands on this processor to experiment and validate these claims?
    Contact Harvest Management Partners using the form below for more information.

FAQ

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