COMPOUND COMPLEX
INSTRUCTION SET COMPUTER
(CCISC, a.k.a. MACROprocessor)
Patented ISA: US 9,405,534 B2 (Aug 2, 2016); Tom Yap, Inventor; 18 claims.
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THE ARCHITECTURE
The CCISC provides superior computing performance without
high clock speeds. It is scalable, adaptable and can be utilized in
ANY bus size (8-bit, 32-bit, n-bit.)
It has a small size with minimal support circuitry, and performance
will improve with pipelining.
A LOOK INSIDE THE CCSIC PROCESSOR
All of the following features support a single-clock-cycle MACRO operation:
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Triple Internal Bus for Compound Instructions
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Dual Channel and Compound Memory
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Independent AGUs for single-cycle advanced addressing modes
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Compounded ALU – the ability to execute an expression every clock cycle
Unlike RISC/ARM-based architectures (above), the CCSIC processor utilizes compound memory and skips the loading / storing of instructions to registers, only using registers for peripherals
and control (below).
RISC vs. CCISC COMPARISON
Decision Branch: X < Y, branch Z
​The operation takes more than one instruction on a RISC architecture.
Each RISC instruction can take more than one cycle. Branch instructions on
the RISC can take a variable number of cycles, making timing less predictable. The CCISC architecture does the entire operation in one instruction,
one cycle, regardless of a branch taken or not.
ARCHITECTURAL DIFFERENTIATORS:
COMPARE ENGINE
Unlike other processor architectures, the CCISC (“MP8” shown above) can execute complex decisions in a single cycle without the need of
an accumulator to compare state changes.
This allows the CCISC to maintain a target sampling rate on a sensor at a much lower clock speed. In the common use case where the processor is asleep most of the time and wakes up to do a quick burst of sampling, the CCISC will be able to complete the task quicker, going back to sleep sooner.
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PERFORMANCE COMPARISON
TEST ENVIRONMENT & TOOLSET
Ensuring a smooth transition for developers.
We use a Standard C Compiler, modified to support our MACROprocessor. SDCC is a retargetable, optimizing Standard C (ANSI C89, ISO C99, ISO C11) compiler suite that targets 8-bit microprocessors.
The Small Device C Compiler is a free-software, partially retargetable C compiler for 8-bit microcontrollers. It is distributed under the GNU General Public License. The package also contains an assembler, linker, simulator and debugger. It uses a SDCC Rev4.2.0 - C Compiler.
